1. Field of the Invention
The present invention relates generally to a field effect transistor and, more particularly, to a field effect transistor capable of high speed operation and to a manufacturing method therefor.
2. Description of the Prior Art
A field effect transistor (hereinafter referred to as FET) has been well known. FIGS. 1A to 1D show the manufacturing process of a conventional FET in a stepwise manner. A silicon oxide film 2a is formed on a P type semiconductor substrate. A silicon layer 3a or a layer of a conductive material such as a metal of high melting point is formed thereon (FIG. 1A). The polysilicon layer 3a and the silicon oxide film 2a are simultaneously etched by a known etching method, and a gate electrode 3 and a gate insulating film 2 are formed (FIG. 1B). A known etching method is disclosed in, for example, "Microfabrication Technique by Gas Plasma Etching Method" H. Komiya et al. Proc. of 7th Conference on Solid State Device 1975, Supplement to Japanese Journal of Applied Physics Vol. 15, p. 19 (1976). N type impurities are implanted from above the semiconductor substrate 1 using the gate electrode 3 as a mask. Thereafter, heat treatment is carried out. Consequently, N.sup.+ impurity layers 4a and 4b are formed on a main surface of the semiconductor substrate 1 in self alignment. The N.sup.+ impurity layers 4a and 4b constitute a source and a drain of a transistor (FIG. 1C). An Al wiring layer is formed connected to the N.sup.+ impurity layers (FIG. 1D). An enlarged view of the gate portion of the FET transistor structured as described above is shown in FIG. 2A. Since the N.sup.+ impurity layers 4a and 4b are formed by heat treatment, the impurities are diffused also in the transverse direction in accordance with the diffusion coefficient of the impurities. Consequently, an overlap portion is generated between the gate electrode 3 and the source.multidot.drain diffusion layers 4. The degree of overlap (the distance .DELTA.L) differs dependent on the type of impurities and on the temperature of heat treatment. An equivalent circuit of FIG. 2A is shown in FIG. 2B.
The overlapping portion (.DELTA.L) constitutes an additional capacitance between the gate and the source-drain as shown in the equivalent circuit of FIG. 2B. Therefore, if this MOS transistor is used in an integrated circuit or the like, the MOS transistor cannot operate at high speed and the power consumption of the MOS transistor becomes large. If the dimension of the overlapping portion becomes large, there will be a so-called short channel effect, causing problems such as the change of threshold voltage of the MOS transistor. Therefore, the overlapping portion is also an obstruction in reducing the size of the MOS transistor.
Besides the above described problem, a conventional FET has a problem of decrease of transconductance. The transconductance is one of the characteristics of the transistor, which means the proportion of the drain current to the gate voltage. FIG. 3 is a schematic diagram showing the electric field and the movement of electrons in a conventional FET. The drain is kept at a constant potential. A plane of equal potential is formed in the vicinity of the drain as shown in the figure. Therefore, an end portion of the drain has a high electric field. If a prescribed potential is applied to the gate of the transistor, a channel region is formed on a main surface of the semiconductor substrate between the source and the drain 4a and 4b, whereby electrons move from the source 4a to the drain 4b. When the electrons reach the high electric field region near the drain, the electrons receive large energy from the electric field, so that the electrons become hot electrons. The hot electrons generated in this manner are trapped near the gate insulating film sandwiched between the gate electrode and the drain region. Consequently, the surfaces of the drain and the channel region become liable to be inverted to the P type. Therefore, the concentration of the N type impurities becomes substantially low and the source resistance of the MOS transistor increases. Normally, when a constant voltage is applied to the gate electrode of the FET, a constant current flows. However, due to the above described reasons, a constant current does not flow even if a constant voltage is applied to the gate.